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Features
* * * * * * *
Single 3-V Supply Voltage High Power-added Efficient Power Amplifier (Pout typically 26.5 dBm) Ramp-controlled Output Power Low-noise Preamplifier (NF typically 1.8 dB) Biasing for External PIN Diode T/R Switch Current-saving Standby Mode Few External Components
DECT SiGe Front End IC U7004B
Electrostatic sensitive device. Observe precautions for handling.
Description
The U7004B is a monolithic SiGe transmit/receive front end IC with power amplifier, 50-W internal matching, low-noise amplifier and T/R switch driver. It is especially designed for operation in TDMA systems like DECT. Due to the ramp-control feature and a very low quiescent current, an external switch transistor for VS is not required. Figure 1. Block Diagram
VS_PA V1_PA
PA PA_IN RAMP LNA LNA_IN TX/RX Standby control T/R Switch driver SWITCH_OUT V2_PA_OUT
LNA_OUT
RX_ON
PU
R_SWITCH
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1
Pin Configuration
Figure 2. Pinning SSO20
R_SWITCH SWITCH_OUT GND1 LNA_IN GND2 V1_PA GND3 GND4 GND5 1 2 3 4 20 19 18 17 PU RX_ON LNA_OUT GND8 VS_LNA PA_IN RAMP VS_PA GND7 GND6
U7004B
5 6 7 8 9 16 15 14 13 12 11
V2_PA_OUT 10
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol R_SWITCH SWITCH_OUT GND1 LNA_IN GND2 V1_PA GND3 GND4 GND5 V2_PA_OUT GND6 GND7 VS_PA RAMP PA_IN VS_LNA GND8 LNA_OUT RX_ON PU Function Resistor to GND sets the PIN diode current Switched current output for PIN diode Ground Low-noise amplifier input Ground Inductor to power supply for power amplifier Ground Ground Ground Inductor to power supply and matching network for power amplifier output Ground Ground Supply voltage for power amplifier Power-ramping control input Power amplifier input Supply-voltage input for low-noise amplifier Ground Low-noise amplifier output RX active high Power-up active high
2
U7004B
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U7004B
Absolute Maximum Ratings
All voltages refer to GND (pins 3, 5, 7, 8, 9, 11, 12 and 17), ESD protection according to ESD-S5.2-1994, Class M1.
Parameters Supply voltage pins 6, 10, 13 and 16 (no RF) Duty cycle PA Burst duration PA Junction temperature Storage temperature Input power PA pin 15 Input power LNA pin 4 Tj Tstg PinPA PinLNA Symbol VS Value 5 50 5 150 -40 to +125 +10 -5 Unit V % ms C C dBm dBm
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 95 Unit K/W
Operating Range
All voltages refer to GND (Pins 3, 5, 7, 8, 9, 11, 12 and 17). The following table represents the sum of all supply currents depending on the TX/RX mode. Power supply points are VS_LNA, VS_PA, V1_PA, V2_PA_OUT.
Parameters Supply voltage pins 6, 10 and 13 Supply voltage pin 16 Supply current TX RX Standby current PU = 0 Ambient temperature Symbol VS VS IS IS IS Tamb -25 Min. 2.7 2.7 Typ. 3.6 3.6 450 8 10 +25 +70 Max. 4.6 4.6 Unit V V mA mA A C
Electrical Characteristics
Test conditions (unless otherwise specified): VS = 3.6 V, Tamb = 25C, pulsed mode, duty cycle 4.17%, ton = 417 s
Parameters Power Amplifier Supply voltage Supply current Supply current Standby current Frequency range Power gain Gain-control range Notes:
(1)
Test Conditions Pins 6, 10 and 13 TX RX (PA off) Standby TX TX, pin 15 to pin 10 TX
Symbol VS IS_TX IS_RX IS_standby f Gp DGp
Min. 2.7
Typ. 3.6 450
Max. 4.6 10 10
Unit V mA A A GHz dB dB
1.88 28 48
1.94
1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: load VSWR = 20:1 (all phases) 10 s, ZG = 50 W 2. With external matching network (see Figure 13 and Figure 14) 3. Low-noise amplifier shall be unconditionally stable
3
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Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 3.6 V, Tamb = 25C, pulsed mode, duty cycle 4.17%, ton = 417 s
Parameters Ramping voltage Ramping current Power-added efficiency Saturated output power Input matching (2) Output matching (2) Harmonics at P 1dB Maximum input power Stability (non harmonic emission) Test Conditions TX, power gain (max), pin 14 TX, power gain (max), pin 14 TX TX, refer to pin 10 TX, pin 15 TX, pin 10 TX, pin 10 Pin 15 TX, pin 10 Pin = 2 dBm, VRAMP = 2 V VSWRout < 10:1 (all phases) Standby, pin 2 RX TX at 100 W TX at 1.2 kW TX at 33 kW All, pin 16 RX TX (control logic active), pin 16 Standby, pin 16 RX RX, pin 4 to pin 18 RX RX, refer to pin 18 RX RX RX = 1, pins 19 and 20 =0 =1 =0 IS_O_standby IS_O_RX IS_O_100 IS_O_1k2 IS_O_33k VS IS IS IS f Gp NF P1dB IIP3 VSWRin VSWRin ViH ViL IiH IiL 2.4 0 40 0 1.88 17 19 1.8 -7 -15 < 2:1 < 2:1 VS 0.5 V V A A 2.0 2.7 1 3 10 3.6 8 300 1 10 1.94 4.6 Symbol VRAMP max IRAMP PAE Psat VSWRin VSWRout 2 fo 3 fo PinPA Min. Typ. 2.1 0.5 30 26.5 < 2:1 < 2:1 -30 10 -60 dBc dBm dBc 2.0 Max. Unit V mA % dBm
T/R Switch Driver (Currently Programmed by External Resistor from R_SWITCH to GND) Switch-out current output Switch-out current output Switch-out current output Switch-out current output Switch-out current output Low-noise Amplifier Supply voltage Supply current Supply current (LNA and control logic) Standby current Frequency range Power gain Noise figure Gain compression 3rd-order input interception point Input matching Output matching Logic Input Levels (RX_ON, PU) High input level Low input level High input current Low input current Notes:
(3)
2 2
A A mA mA mA V mA A A GHz dB dB dBm dBm
1. Power amplifier shall be unconditionally stable, maximum duty cycle 50%, maximum load mismatch and duration: load VSWR = 20:1 (all phases) 10 s, ZG = 50 W 2. With external matching network (see Figure 13 and Figure 14) 3. Low-noise amplifier shall be unconditionally stable
4
U7004B
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U7004B
Control Logic
Table 1. Control Logic for LNA and T/R Switch Driver
Operation Mode Standby TX RX PU 0 1 1 RX_ON 0 0 1
Figure 3. Output Power versus Ramp Voltage
30
20
Pout (dBM)
10
0
-10
-20 0.0 0.5 1.0 1.5 2.0 2.5 3.0
VRAMP (V)
Input/Output Circuits
Figure 4. Input Circuit PA_IN/VS_PA
13 VS_PA
15 PA_IN
17 GND1
5
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Figure 5. Input Circuit RAMP/VS_PA
13 VS_PA
14 RAMP
7 GND7
Figure 6. Input Circuit V1_PA
6 V1_PA
8 GND3
Figure 7. Input/Output Circuit V2_PA
10 V2_PA_OUT
8 GND5
6
U7004B
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U7004B
Figure 8. Input Circuit LNA_IN/VS_LNA
16 VS_LNA
4 LNA_IN 3 GND1
Figure 9. Output Circuit LNA_OUT
16 VS_LNA
18 LNA_OUT
5 GND2
7
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Figure 10. Input Circuit SWITCH_OUT/R_SWITCH
13 VS_PA
2 SWITCH_OUT 1 R_SWITCH
17 GND8
Figure 11. Input Circuit RX_ON
16 VS_LNA
19 RX_ON
Figure 12. Input Circuit PU
16 VS_LNA
20 PU
8
U7004B
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U7004B
Typical Application Circuit
Figure 13. Typical Schematic
LNA_OUT PU RX_ON PCB 20 19 18 17 16 15 14 13 12 11 PA_IN RAMP
TX/RX standby control TX
U7004B
LNA 1 2 3 4 5 6 7 8 9
PA 10 PCB
diel. BPF
PCB VS PCB Microstripline l/4
Antenna
9
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Figure 14. U7004B Application Board Schematic
Figure 15. U7004B Application Board Layout
LNA_OUT PA_IN RAMP
DECT Frontend
100 pF
0R
2.7 nH 2.7 pF 0R
RX_ON
4.7 mF
0R
1.2 pF 1.0 pF 0R 0R 56 pF
V1_PA 56pF 1nF 1mF
15nH 0R Components: - 3 Inductors (Pins 10,13,15) - 16 Capacitors - 1 Resistor (Pin 1)
0R
V2_PA VS_PA GND
0R
2.7 k 390 0R
0R LNA_IN
PA
PA_OUT
10
U7004B
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SWITCH_OUT
4.7 mF
GND
LNA
22nH
1 nF
VS_LNA
0R
56 pF
56 pF
PU
56pF
U7004B
Ordering Information
Extended Type Number U7004B-MFS U7004B-MFSG3 Package SSO20 SSO20 Remarks Tube Taped and reeled
Package Information
Package SSO20
Dimensions in mm
6.75 6.50 5.7 5.3 4.5 4.3
1.30 0.25 0.65 5.85 20 11 0.15 0.05 0.15 6.6 6.3
technical drawings according to DIN specifications
1
10
11
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4713A-DECT-07/03 xM

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